The EFR32FG13 highlighted features are listed below.

■ Low Power Wireless System-on-Chip
• High Performance 32-bit 40 MHz ARM Cortex®-M4 with DSP instruction and floating-point unit for efficient signal processing
• Embedded Trace Macrocell (ETM) for advanced debugging
• 512 kB flash program memory
• 64 kB RAM data memory
• 2.4 GHz and Sub-GHz radio operation
• Transmit power:
• 2.4 GHz radio: Up to 19 dBm
• Sub-GHz radio: Up to 20 dBm

■ Low Energy Consumption
• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz
• 9.5 mA RX current at 1 Mbps, GFSK, 2.4 GHz
• 10.3 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz
• 8.5 mA TX current at 0 dBm output power at 2.4 GHz
• 35.3 mA TX current at 14 dBm output power at 868 MHz
• 69 μA/MHz in Active Mode (EM0)
• 1.3 μA EM2 DeepSleep current (16 kB RAM retention and RTCC running from LFRCO)

■ High Receiver Performance
• -94.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz
• -102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz
• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz
• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz
• -107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz
• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz

■ Supported Modulation Formats
• 2/4 (G)FSK with fully configurable shaping
• BPSK / DBPSK TX
• OOK / ASK
• Shaped OQPSK / (G)MSK
• Configurable DSSS and FEC

■ Supported Protocols
• Proprietary Protocols
• Wireless M-Bus
• Selected IEEE 802.15.4g SUN-FSK PHYs
• Low Power Wide Area Networks

■ Suitable for Systems Targeting Compliance With:
• FCC Part 90.210 Mask D, FCC part 15.247, 15.231, 15.249
• ETSI Category I Operation, EN 300 220, EN 300 328
• ARIB T-108, T-96
• China regulatory

■ Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2 × Analog Comparator (ACMP)
• 2 × Digital to Analog Converter (VDAC)
• 3 × Operational Amplifier (Opamp)
• Digital to Analog Current Converter (IDAC)
• Low-Energy Sensor Interface (LESENSE)
• Multi-channel Capacitive Sense Interface (CSEN)
• Up to 32 pins connected to analog channels (APORT) shared between analog peripherals
• Up to 32 General Purpose I/O pins with output state retention and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2 × 16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• 1 × 32-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up from any Energy Mode
• 16-bit Pulse Counter with asynchronous operation
• 2 × Watchdog Timer with dedicated RC oscillator
• 3 × Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• Low Energy UART (LEUART™)
• 2 × I2C interface with SMBus support and address recognition in EM3 Stop

■ Wide Operating Range
• 1.8 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA load current for system
• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C) temperature grades available

■ Support for Internet Security
• General Purpose CRC
• True Random Number Generator
• 2 × Hardware Cryptographic Acceleration for AES 128/256, SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC

■ QFN32 5x5 mm Package

■ QFN48 7x7 mm Package